1. Field of the Invention
The present invention relates to semiconductor structures, and particularly to a deep trench capacitor.
2. Background of Invention
Deep trenches, typically having a depth exceeding 1 micron, in contrast to shallow trenches having a depth less than 1 micron, are employed in the semiconductor industry to provide a variety of useful devices including a deep trench capacitor. The deep trenches may be utilized in a stand-alone semiconductor circuit such as a dynamic random access memory (DRAM) circuit to provide deep trench capacitors, or may be utilized as an embedded circuit component of a semiconductor chip that also includes other semiconductor circuits such as a processor core or other logic circuits. Particularly, embedded deep trench capacitors may be used to enable an embedded memory device, for example, an embedded dynamic random access memory (eDRAM) cell, a passive component of a radio frequency (RF) circuit, or a decoupling capacitor that provides a stable voltage supply in a semiconductor circuit.
Semiconductor-on-insulator (SOI) substrates are employed in the semiconductor industry for performance benefits due to reduced capacitive coupling between semiconductor devices and the bulk portion of the substrate. The reduced capacitive coupling may be provided by a buried insulator layer. The buried insulator layer separates a bulk substrate below from a SOI layer above and may include any of several known dielectric materials, for example, oxides, nitrides and oxynitrides of silicon. The SOI layer may be considered the active layer where semiconductor devices may be formed. High performance logic chips are frequently manufactured on a SOI substrate to provide enhanced performance over devices having comparable dimensions and manufactured on a bulk substrate.
Generally, deep trench capacitors may include two electrical conductors separated by an insulator. One electrical conductor, commonly referred to as a buried plate, may typically be formed in the bulk substrate. The insulator, which may be referred to as a node dielectric, may be formed within the deep trench on top of the buried plate. The other electrical conductor, which may be referred to as an inner electrode, may be formed within the deep trench on top of the node dielectric. Therefore, the deep trench capacitor may include the inner electrode and the buried plate separated by the node dielectric. The conductors, for example the buried plate and the inner electrode, may preferably be very conductive.
Typical fabrication of a deep trench capacitor may begin by etching a deep trench in a pre-existing SOI substrate. The buried plate, the node dielectric, and the inner electrode may then be formed within the deep trench to form the deep trench capacitor. The buried plate may typically be formed from a portion of the bulk substrate below the buried insulator layer. Doing so may present challenges because the bulk substrate, which may typically include undoped silicon having poor conductivity, must be heavily doped to form the very conductive buried plate. Careful attention must be paid not to introduce unwanted dopants into the SOI layer above the buried insulator layer. It may be desirable to prevent the diffusion of unwanted dopants into the SOI layer, a active layer, because the diffusion of unwanted dopants may caused detrimental effects, if not failures, to the semiconductor devices subsequently formed in the SOI layer. Therefore, special techniques may be used to mask or protect the SOI layer during doping of the bulk substrate to form the buried plate.
In view of the above, methods of manufacturing a deep trench capacitor in a SOI substrate while minimizing or eliminating the risk of introducing dopants in the SOI layer may be desirable.